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(parent: d2b61ed) | patch
cxl/core: Track port depth
authorBen Widawsky <ben.widawsky@intel.com>
Mon, 24 Jan 2022 00:29:53 +0000 (16:29 -0800)
committerDan Williams <dan.j.williams@intel.com>
Wed, 9 Feb 2022 06:57:29 +0000 (22:57 -0800)
commit53fa1bff3426344d466d91e81f076eab677d0ece
treee29317f8652ba42a4da2a3b98d90c11d6b65865ctree | snapshot
parentd2b61ed2ff63fd9f294db8399c7a680ea7fe8a23commit | diff
cxl/core: Track port depth

In preparation for proving CXL subsystem usage of the device_lock()
order track the depth of ports with the expectation that  shallower port
locks can be held over deeper port locks.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/port.c diff | blob | history
drivers/cxl/cxl.h diff | blob | history
Domain: System / Kernel;