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clk: renesas: r9a07g044: Fix OSTM1 module clock name
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 2 May 2022 12:35:02 +0000 (14:35 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commit53c58c08b454aea3c9c9ceda600567436134e6a2
tree7280388f2c583d2ac90ca29a10dc4f307a13098ctree | snapshot
parent84c9829d16d86a09703d9f2c8dac3816c56bcdcdcommit | diff
clk: renesas: r9a07g044: Fix OSTM1 module clock name

Fix a typo in the name of the "ostm1_pclk" clock.
This change has no run-time impact.

Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
Domain: System / Kernel;