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drm/i915: Set i9xx lvds clock limits according to specifications
authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
Wed, 13 Feb 2013 21:20:21 +0000 (22:20 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 19 Feb 2013 23:21:46 +0000 (00:21 +0100)
commit53a7d2d15ef45fb892defaf624ad6db7d528d8ac
tree06e242f35812c3b00d5fbfa079f7343de57b0d4ctree | snapshot
parent876a8cdf92b23d268275cdce4397df0c37dac3fecommit | diff
drm/i915: Set i9xx lvds clock limits according to specifications

The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
Domain: System / Kernel;