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(parent: ea0b241) | patch
clk: qcom: msm8960: fix ce3_core clk enable register
authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Mon, 22 Feb 2016 11:43:39 +0000 (11:43 +0000)
committerSasha Levin <sasha.levin@oracle.com>
Mon, 11 Jul 2016 03:07:17 +0000 (23:07 -0400)
commit5356deeafda4e139a44f6f82a99439d93a7b84cf
treeb8538a3b54c23e10df88629c0651b2b27aa2517atree | snapshot
parentea0b24134918a838f1ff94ac4707d3dcc637630ccommit | diff
clk: qcom: msm8960: fix ce3_core clk enable register

[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
drivers/clk/qcom/gcc-msm8960.c diff | blob | history
Domain: System / Kernel;