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(parent: ed0ffb5) | patch
drm/amd/display: adopt DP2.0 LT SCR revision 8
authorWenjing Liu <wenjing.liu@amd.com>
Mon, 14 Jun 2021 22:31:21 +0000 (18:31 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Oct 2021 18:26:17 +0000 (14:26 -0400)
commit5354b2bd28082032644a644448ce6fa3fb476cbe
tree10525ebe5598790de991aae2db91964b582c9c3dtree | snapshot
parented0ffb5dcde95a13bd0208db0b65416e8406699acommit | diff
drm/amd/display: adopt DP2.0 LT SCR revision 8

[how]
revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment
in one 5 byte write aux transaction.
It specifies to read aux rd interval value as soon as we turn on TPS1
pattern.

Cc: Wayne Lin <wayne.lin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c diff | blob | history
Domain: System / Kernel;