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(parent: d60ae47) | patch
[AArch64] Generate AND in place of CSEL for predicated CTTZ
authorRahul Anand R <rahul@rrlogic.co.in>
Fri, 20 May 2022 12:41:32 +0000 (13:41 +0100)
committerDavid Green <david.green@arm.com>
Fri, 20 May 2022 12:41:32 +0000 (13:41 +0100)
commit534ea8bca51d9e2673a7170c34f1d91b17fabda2
treeff0f16929a1d21c3e6f2efbc114d13aa431bb961tree | snapshot
parentd60ae47f9dabcbc42b894f988b51d4643447b599commit | diff
[AArch64] Generate AND in place of CSEL for predicated CTTZ

This patch implements a for a target specific optimization that replaces
the cmp and csel from cttz with an and mask.

Recommitted with a fix for truncated value sizes.

Differential Revision: https://reviews.llvm.org/D123782
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll [new file with mode: 0644] blob
Domain: System / Toolchain;