review.tizen.org Git - platform/kernel/linux-rpi.git/commit

Merge tag 'x86_bugs_pbrsb' of git://git./linux/kernel/git/tip/tip

Pull x86 eIBRS fixes from Borislav Petkov:
"More from the CPU vulnerability nightmares front:

  Intel eIBRS machines do not sufficiently mitigate against RET
  mispredictions when doing a VM Exit therefore an additional RSB,
  one-entry stuffing is needed"

* tag 'x86_bugs_pbrsb' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/speculation: Add LFENCE to RSB fill sequence
  x86/speculation: Add RSB VM Exit protections

author	Linus Torvalds <torvalds@linux-foundation.org>
	Tue, 9 Aug 2022 16:29:07 +0000 (09:29 -0700)
committer	Linus Torvalds <torvalds@linux-foundation.org>
	Tue, 9 Aug 2022 16:29:07 +0000 (09:29 -0700)
commit	5318b987fe9f3430adb0f5d81d07052fd996835b
tree	35b0c7287c7ca98d3a5302aa72e948e3fbec2000	tree \| snapshot
parent	eb555cb5b794f4e12a9897f3d46d5a72104cd4a7	commit \| diff
parent	ba6e31af2be96c4d0536f2152ed6f7b6c11bca47	commit \| diff

arch/x86/include/asm/cpufeatures.h	diff1 \|	diff2 \|	blob \| history
arch/x86/include/asm/msr-index.h	diff1 \|	diff2 \|	blob \| history
arch/x86/include/asm/nospec-branch.h	diff1 \|	diff2 \|	blob \| history