re PR target/80510 (Optimize Power7/power8 Altivec load/stores)
authorMichael Meissner <meissner@linux.vnet.ibm.com>
Thu, 18 May 2017 19:34:13 +0000 (19:34 +0000)
committerMichael Meissner <meissner@gcc.gnu.org>
Thu, 18 May 2017 19:34:13 +0000 (19:34 +0000)
commit52e14b96bd537b5431c577213c14db4686397d71
tree3fdb1db7c15c1b1ec369836778fa8f0997dceae2
parent4287da829c9697c58131666447bf8f707bd8b635
re PR target/80510 (Optimize Power7/power8 Altivec load/stores)

[gcc]
2017-05-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/80510
* config/rs6000/predicates.md (simple_offsettable_mem_operand):
New predicate.

* config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator.
(define_peephole2 for Altivec d-form load): Add peepholes to catch
cases where the register allocator uses a move and an offsettable
memory operation to/from a FPR register on ISA 2.06/2.07.
(define_peephole2 for Altivec d-form store): Likewise.

[gcc/testsuite]
2017-05-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/80510
* gcc.target/powerpc/pr80510-1.c: New test.
* gcc.target/powerpc/pr80510-2.c: Likewise.

From-SVN: r248254
gcc/ChangeLog
gcc/config/rs6000/predicates.md
gcc/config/rs6000/rs6000.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/pr80510-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/pr80510-2.c [new file with mode: 0644]