intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP
authorJordan Justen <jordan.l.justen@intel.com>
Thu, 9 Dec 2021 21:05:29 +0000 (13:05 -0800)
committerJordan Justen <jordan.l.justen@intel.com>
Tue, 14 Dec 2021 00:59:37 +0000 (16:59 -0800)
commit52a55f097f3105e25e778f173c2133bfc00478ad
treee9e442117226bf608684f4f4acc4472992b7a3de
parent211e0606c7805dd1ce870d736681078985d657d7
intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP

Based on Rafael's:
 * "nir/lower_tex: Add option to lower offset for tg4 too."
 * "intel/compiler: Lower offsets for tg4 on gen9+."
 * "WIP: Do not lower basic offsets."
 * "WIP: intel/compiler: Enable lowering offsets restriction."

But, with these changes:
 * Fixed range checking to be signed 4 bits
 * Converted to filter
 * Apply only to gfx12.5+
 * Use nir_src_is_const / nir_src_comp_as_int (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>
src/intel/compiler/brw_nir.c