broadcom/cle: update the packet definitions for new generation v71

broadcom/cle: update the packet definitions for new generation v71

Using as reference the spec for 7.1.5. This include totally new
packets, and redefine some that already existed on v42.

Full list:
 * Add Depth Bounds Test Limits
 * Redefine Tile Binning Mode Cfg
 * Redefine Cfg Bits. There are some changes on the fields:
   * Line Rasterization is now 1 bit size
   * Depth Bounds Enable (that takes one of the bits of Line Rasterization)
   * Early-Z/Early-Z updates enable bits (16-17) figure now as reserved.
   * New Z-Clipping mode field
 * Redefine Tile Rendering Mode Cfg (Common). Changes with respect to v42:
   * New log2 tile height/width fields starting at bit 52/55
   * Due those two news, end pad is smaller
   * sub-id has now a size of 3. Bit 4 is reserved.
   * Number of render targets: this field max value is now 7 (not
     reflected on the xml).
   * Maximum BPP is removed on v71 (now bits 40-41 are reserved)
   * Depth Buffer disable: on bit 44
 * Update Store Tile Buffer General
 * Adding Cfg Render Target Part1/2/3 packets: they replace v4X "Tile
   Rendering Mode Cfg (Color)" (real name "Rendering Configuration
   (Render Targets Config)"), "Tile Rendering Mode Cfg (Clear Colors
   Part1)", "Tile Rendering Mode Cfg (Clear Colors Part2)", and "Tile
   Rendering Mode Cfg (Clear Colors Part3)". On those old versions,
   the first packet is used to configure 4 render targets. Now that 8
   are supported, invididual per-render-target are used.
 * Update ZS clear values packet.
 * Add new v71 output formats
 * Define Clear Render Targets (Replaces Clear Tile Buffers from v42)
 * Redefine GL Shader State Record. Changes copared with v42:
   * Fields removed:
     * "Coordinate shader has separate input and output VPM blocks"
       (reserved bit now)
     * "Vertex shader has separate input and output VPM blocks"
       (reserved bit now)
     * "Address of table of default attribute Values." (we needed to
       change the start position for all the following fields)
   * New field:
     * "Never defer FEP depth writes to fragment shader auto Z writes
        on scoreboard conflict"
 * Redefine clipper xy scaling: Now it uses 1/64ths of pixels, instead
   of 1/256ths
 * Update texture shader state.
   * Notice we don't use an address type for these fields in the XML
     description. This is because the addresses are 64-bit aligned
     (even though the PRM doesn't say it) which means the 6 LSB bits
     are implicitly 0, but the fields are encoded before the 6th bit
     of their starting byte, so we can't use the usual trick we do
     with address types where the first 6 bits in the byte are
     implicitly overwritten by other fields and we have to encode this
     manually as a uint field. This would mean that if we had an
     actual BO we would also need to add it manually to the job's
     list, but since we don't have one, we don't have to do anything
     about it.
   * Add new RB_Swap field for texture shader state
   * Document Cb/Cr addresses as uint fields in texture shader state
 * Fixup Blend Config description: we now support 8 RTs.
 * TMU config parameter 2 has new fields
 * Add new clipper Z without guardband packet in v71
 * Add enums for the Z clip modes accepted in v71
 * Fix texture state array stride packing for V3D 7.1.5

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>