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[PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD
authorQingShan Zhang <qshanz@cn.ibm.com>
Sat, 12 Sep 2020 02:42:22 +0000 (02:42 +0000)
committerQingShan Zhang <qshanz@cn.ibm.com>
Sat, 12 Sep 2020 02:42:22 +0000 (02:42 +0000)
commit528554c39b098e2d9a9c7ec51c77717aa07db2a2
treea2003a8f72da8e7a394472b856aa141f801e9173tree | snapshot
parent0e0d93e2f09a3e84cee0e77f0f2510001c2f064acommit | diff
[PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD

From ISA, fcmpu will raise the Floating-Point Invalid Operation
Exception (SNaN) if either of the operands is a Signaling NaN by setting
the bit VXSNAN. But the instruction description didn't set the
mayRaiseFPException which might have impact on the scheduling or some
backend optimization.

Reviewed By: qiucf

Differential Revision: https://reviews.llvm.org/D83937
llvm/lib/Target/PowerPC/PPCInstrInfo.td diff | blob | history
llvm/test/CodeGen/PowerPC/nofpexcept.ll [new file with mode: 0644] blob
Domain: System / Toolchain;