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[LV] Fix miscompile due to srem/sdiv speculation safety condition
authorPhilip Reames <preames@rivosinc.com>
Tue, 19 Jul 2022 18:42:55 +0000 (11:42 -0700)
committerPhilip Reames <listmail@philipreames.com>
Wed, 20 Jul 2022 12:35:23 +0000 (05:35 -0700)
commit523a526a024fb2835c998d1c054698cc16da87f4
tree3dedb67ec816010029469e20a7d5363788a22241tree | snapshot
parentf8c13754af55c1dcee3ee0a57580b43c422662c4commit | diff
[LV] Fix miscompile due to srem/sdiv speculation safety condition

An srem or sdiv has two cases which can cause undefined behavior, not just one. The existing code did not account for this, and as a result, we miscompiled when we encountered e.g. a srem i64 %v, -1 in a conditional block.

Instead of hand rolling the logic, just use the utility function which exists exactly for this purpose.

Differential Revision: https://reviews.llvm.org/D130106
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp diff | blob | history
llvm/test/Transforms/LoopVectorize/RISCV/scalable-divrem.ll diff | blob | history
Domain: System / Toolchain;