clk: mediatek: update clock driver of MT2712
authorWeiyi Lu <weiyi.lu@mediatek.com>
Fri, 14 Dec 2018 02:04:17 +0000 (10:04 +0800)
committerStephen Boyd <sboyd@kernel.org>
Tue, 5 Feb 2019 21:28:04 +0000 (13:28 -0800)
commit51ff86dd1069a9ea52672efb20b89dbaff6dffe1
treeb2d353b0726ed3d5c80f417a1a48269248f58750
parentc3424f59a0cb994a098c3701bf14617580a18290
clk: mediatek: update clock driver of MT2712

According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/clk-mt2712.c