[mips] Place certain 64 bit FPU instructions in their own decoder namespace
authorSimon Dardis <simon.dardis@imgtec.com>
Thu, 5 Oct 2017 10:27:37 +0000 (10:27 +0000)
committerSimon Dardis <simon.dardis@imgtec.com>
Thu, 5 Oct 2017 10:27:37 +0000 (10:27 +0000)
commit51a7ae2a2936dd686115950871cb599cf47cf089
treeb5662b30e602ab0041638809dac208cd825007b4
parent59428d182f6074363588beaecdacbbd1eb842bb8
[mips] Place certain 64 bit FPU instructions in their own decoder namespace

Previously, instructions that were defined to use the FGR64 register class
were associated with the Mips64 table which was incorrect.

Reviewers: nitesh.jain, atanasyan

Differential Revision: https://reviews.llvm.org/D38454

llvm-svn: 314976
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/lib/Target/Mips/MipsCondMov.td
llvm/lib/Target/Mips/MipsInstrFPU.td
llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt