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[AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.
authorChad Rosier <mcrosier@codeaurora.org>
Fri, 10 Apr 2015 13:19:27 +0000 (13:19 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Fri, 10 Apr 2015 13:19:27 +0000 (13:19 +0000)
commit518659d9b454a69abce3c81649aba4c8a89e071b
tree85a0db90969f90605160f9b03dd1bda723c0dec6tree | snapshot
parenta82c87604582e58717f502bf9070578b7f9bfd0dcommit | diff
[AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.

Using SchedAliases is convenient and works well for latency and resource
lookup for instructions.  However, this creates an entry in
AArch64WriteLatencyTable with a WriteResourceID of 0, breaking any
SchedReadAdvance since the lookup will fail.

http://reviews.llvm.org/D8043
Patch by Dave Estes <cestes@codeaurora.org>!

llvm-svn: 234594
llvm/lib/Target/AArch64/AArch64SchedA57.td diff | blob | history
Domain: System / Toolchain;