clk: tegra20: Turn EMC clock gate into divider
authorDmitry Osipenko <digetx@gmail.com>
Sun, 21 Oct 2018 18:30:50 +0000 (21:30 +0300)
committerThierry Reding <treding@nvidia.com>
Thu, 8 Nov 2018 11:47:17 +0000 (12:47 +0100)
commit514fddba845ed3a1b17e01e99cb3a2a52256a88a
treee2e879b87eaf6c4b85fbb1ef77a1743c31e4e3a2
parent651022382c7f8da46cb4872a545ee1da6d097d2a
clk: tegra20: Turn EMC clock gate into divider

Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c