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(parent: 0eadd36) | patch
gpio: exar: access MPIO registers on cascaded chips
authorQingtao Cao <qingtao.cao.au@gmail.com>
Fri, 2 Sep 2022 06:14:34 +0000 (16:14 +1000)
committerBartosz Golaszewski <brgl@bgdev.pl>
Sun, 4 Sep 2022 20:25:10 +0000 (22:25 +0200)
commit5134272f9f3f71d4e1f3aa15cb09321af49b3646
treefed7562d45a8614dfe4908aa777752aa84bb398ftree | snapshot
parent0eadd36d9123745f70e233a9d93951d05ca1916acommit | diff
gpio: exar: access MPIO registers on cascaded chips

When EXAR xr17v35x chips are cascaded in order to access the MPIO registers
(part of the Device Configuration Registers) of the secondary chips, an offset
needs to be applied based on the number of primary chip's UART channels.

Signed-off-by: Qingtao Cao <qingtao.cao@digi.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
drivers/gpio/gpio-exar.c diff | blob | history
Domain: System / Kernel;