[AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.
authorAmara Emerson <aemerson@apple.com>
Tue, 23 Jul 2019 22:05:13 +0000 (22:05 +0000)
committerAmara Emerson <aemerson@apple.com>
Tue, 23 Jul 2019 22:05:13 +0000 (22:05 +0000)
commit511f7f5785e58a75fd82675336fa7fc90ba45c76
treea4fff33fad3c51ccd5fae9672889196d50666b67
parent78b1e777f59a26d667d6a5258138cc09cf146c18
[AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.

We need to be able to load and store s128 for memcpy inlining, where we want to
generate Q register mem ops. Making these legal also requires that we add some
support in other instructions. Regbankselect should also know about these since
they have no GPR register class that can hold them, so need special handling to
live on the FPR bank.

Differential Revision: https://reviews.llvm.org/D65166

llvm-svn: 366857
12 files changed:
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir [deleted file]
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir