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(parent: 0caf5f4) | patch
iommu/arm-smmu: Convert GR1 registers to bitfields
authorRobin Murphy <robin.murphy@arm.com>
Thu, 15 Aug 2019 18:37:24 +0000 (19:37 +0100)
committerWill Deacon <will@kernel.org>
Mon, 19 Aug 2019 15:52:47 +0000 (16:52 +0100)
commit5114e96cb27ed71559f2b674bb3c6ee14eafe9f9
treef1d3f85e676cc77e1087f6bd00ff6d4c28226602tree | snapshot
parent0caf5f4e84fe0a870917984abf1f0eb29fa6e375commit | diff
iommu/arm-smmu: Convert GR1 registers to bitfields

As for GR0, use the bitfield helpers to make GR1 usage a little cleaner,
and use it as an opportunity to audit and tidy the definitions. This
tweaks the handling of CBAR types to match what we did for S2CR a while
back, and fixes a couple of names which didn't quite match the latest
architecture spec (IHI0062D.c).

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm-smmu-regs.h diff | blob | history
drivers/iommu/arm-smmu.c diff | blob | history
Domain: System / Kernel;