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[AArch64] GlobalIsel codegen for gpr CTZ
authorTies Stuij <ties.stuij@arm.com>
Wed, 21 Dec 2022 11:08:55 +0000 (11:08 +0000)
committerTies Stuij <ties@stuij.se>
Wed, 21 Dec 2022 11:31:50 +0000 (11:31 +0000)
commit50ddc8cca631bb6bffd69804b9b25d89a1a0bce2
treea1f9ac048cd66ffdd8e66c53a4fef8da7f8ea16ftree | snapshot
parent3a3f725a3cdc44cacb8f9847404a148ee056c913commit | diff
[AArch64] GlobalIsel codegen for gpr CTZ

If feature CSSC is available, CTTZ intrinsics are lowered using the CTZ
instruction when using GlobalIsel.

spec:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/CTZ--Count-Trailing-Zeros-

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D139418
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/select-cttz.mir [new file with mode: 0644] blob
Domain: System / Toolchain;