Add support for branch forms of ALU instructions to Cortex-A57 model
authorEvgeny Leviant <eleviant@accesssoftek.com>
Tue, 24 Nov 2020 08:43:51 +0000 (11:43 +0300)
committerEvgeny Leviant <eleviant@accesssoftek.com>
Tue, 24 Nov 2020 08:43:51 +0000 (11:43 +0300)
commit50bd686695ac2ca25996be7994808f93a2b753c5
tree13824f02f9a9d65d7ff8e479bc234cb23d6fa3ca
parentc3914bf28e3902c0e039eb31d2f36112a606dc58
Add support for branch forms of ALU instructions to Cortex-A57 model

Patch fixes scheduling of ALU instructions which modify pc register. Patch
also fixes computation of mutually exclusive predicates for sequences of
variants to be properly expanded

Differential revision: https://reviews.llvm.org/D91266
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSchedule.td
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
llvm/utils/TableGen/CodeGenSchedule.cpp
llvm/utils/TableGen/SubtargetEmitter.cpp