drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming
authorGeorge Shen <george.shen@amd.com>
Thu, 11 Aug 2022 02:06:17 +0000 (22:06 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 30 Aug 2022 20:57:23 +0000 (16:57 -0400)
commit507fd7c400032b126747a5ae8cca2816d73f009a
tree29a03469b2bda46d38dec966deefb9c12ca54bf7
parent47e04eed84bb07cc5b54462752a4bc7286ab8197
drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming

[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.

Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-to-1 with
HPO stream encoder instance. This is not always
guaranteed and can result in blackscreen.

[How]
Program the correct dpstreamclk instance with
the correct dtbclk_p source.

Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c