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RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
authorYash Shah <yash.shah@sifive.com>
Thu, 10 Dec 2020 10:28:03 +0000 (15:58 +0530)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Fri, 8 Jan 2021 01:28:27 +0000 (17:28 -0800)
commit507308b8ccc90d37b07bfca8ffe130435d6b354f
tree46b79f3cbf7ce3c59ae35f362ef1cf059de3e071tree | snapshot
parentaf951c3a113bc2cc0419e39f5752ca77f7ddf228commit | diff
RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740

SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
drivers/soc/sifive/sifive_l2_cache.c diff | blob | history
Domain: System / Kernel;