drm/i915/xehp: Add Compute CS IRQ handlers
authorMatt Roper <matthew.d.roper@intel.com>
Tue, 1 Mar 2022 23:15:39 +0000 (15:15 -0800)
committerMatt Roper <matthew.d.roper@intel.com>
Wed, 2 Mar 2022 14:45:17 +0000 (06:45 -0800)
commit505c4857fb13fb0ea88a42b843c91d0b9f8231fe
tree71cd1db01bfdff0e7fe4136523bf3f814c30348f
parent4b88ad503d6d2ea11891a355e656bf428ec815e6
drm/i915/xehp: Add Compute CS IRQ handlers

Add execlists and GuC interrupts for compute CS into existing IRQ handlers.

All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.

CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.

BSpec: 50844, 54029, 54030, 53223, 53224.
Original-author: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-4-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_gt_irq.c
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/i915_drv.h