drm/i915/cmdparser: Limit clflush to active cachelines
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 10 Mar 2017 11:55:18 +0000 (11:55 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 10 Mar 2017 13:02:34 +0000 (13:02 +0000)
commit504ae4024131c5a01c3ce8382d49b801375e039c
tree7d79d1adcac7c7e74d6f3d91a691273f605fb5c9
parentb8473050805f35add97f3ff57570d55a01808df5
drm/i915/cmdparser: Limit clflush to active cachelines

We only need to clflush those cachelines that we have validated to be
read by the GPU. Userspace typically fills the batch length in
correctly, the exceptions tend to be explicit tests within igt.

v2: Use ptr_mask_bits() to make Mika happy
v3: cmd is not advanced on MI_BBE, so make sure to include an extra
dword in the clflush.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170310115518.13832-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_cmd_parser.c