mmc: bfin_sdh: Add support for new RSI controller in bf60x
authorSonic Zhang <sonic.zhang@analog.com>
Wed, 8 Aug 2012 04:13:32 +0000 (00:13 -0400)
committerChris Ball <cjb@laptop.org>
Tue, 4 Sep 2012 17:58:18 +0000 (13:58 -0400)
commit4ffdcf0469f1e7e47476ee410e8dfbc6aba61b65
tree53ddf5d1db62878ef37460a5f2bcbf49a3169424
parent0462566b1e3129b2920b63b62a653b70a1bc36fa
mmc: bfin_sdh: Add support for new RSI controller in bf60x

In BF60x RSI controller:
1) MMR read/write width differs.
2) PWR and CTL MMRs are merged to together.
3) ROD and PD_DAT3 bit masks are obsolete.
4) New RSI block size MMR is defined.
5) The definition of DMA descriptor set size is changed.
6) set_ios should powers up controller in 2 steps.

In addition, this patch cleans up the spin locks.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
drivers/mmc/host/bfin_sdh.c