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(parent: 7eecdd4) | patch
dt-bingings:riscv_timer: timebase-frequency is 4M.
authorsamin <samin.guo@starfivetech.com>
Sat, 14 May 2022 11:04:01 +0000 (19:04 +0800)
committersamin <samin.guo@starfivetech.com>
Sun, 15 May 2022 10:57:04 +0000 (18:57 +0800)
commit4fd9a3e7eba036eac5a972b268c38f3ed811e74d
treec6818aa166b5c525c96b620618a58eba622682dctree | snapshot
parent7eecdd45679813e92043657a5c05f758118421a0commit | diff
dt-bingings:riscv_timer: timebase-frequency is 4M.

JH7110 SOC riscv_timer frequency is 4M.
FPGA is 2M.

Signed-off-by: samin <samin.guo@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110-common.dtsi diff | blob | history
arch/riscv/boot/dts/starfive/jh7110-fpga.dts diff | blob | history
Domain: System / Kernel;