Complete the SPE instruction set patterns
authorJustin Hibbits <jrh29@alumni.cwru.edu>
Wed, 18 Jul 2018 04:24:57 +0000 (04:24 +0000)
committerJustin Hibbits <jrh29@alumni.cwru.edu>
Wed, 18 Jul 2018 04:24:57 +0000 (04:24 +0000)
commit4fa4fa6a73a7829494df8272ef49825fb2066d1a
tree4ca3a2c58f117e34257c53ef95453bd06027d058
parentceb3cd96f7eaacb206856fdb6e93e1a0d682955b
Complete the SPE instruction set patterns

This is the lead-up to having SPE codegen.  Add the rest of the
instructions, along with MC tests.

Differential Revision:  https://reviews.llvm.org/D44829

llvm-svn: 337346
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrSPE.td
llvm/lib/Target/PowerPC/PPCSchedule.td
llvm/lib/Target/PowerPC/PPCScheduleE500.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-e500.txt
llvm/test/MC/PowerPC/ppc64-encoding-spe.s