clk: tegra: Fix clock sources for Tegra210 EMC
authorJon Hunter <jonathanh@nvidia.com>
Fri, 18 Dec 2015 13:45:28 +0000 (13:45 +0000)
committerThierry Reding <treding@nvidia.com>
Tue, 2 Feb 2016 14:49:30 +0000 (15:49 +0100)
commit4f8d44403079991a29e69f6aa25bb718ead418cb
tree48713f62eead2fd1be115b342c46cd85076300c1
parent29569941688cdf647f953b2eb073aa6ec9dd3fc1
clk: tegra: Fix clock sources for Tegra210 EMC

The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.

Also add the additional pll_p clock source for the EMC.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c