AMDGPU/SI: Assembler: Unify parsing/printing of operands.
authorNikolay Haustov <Nikolay.Haustov@amd.com>
Fri, 29 Apr 2016 09:02:30 +0000 (09:02 +0000)
committerNikolay Haustov <Nikolay.Haustov@amd.com>
Fri, 29 Apr 2016 09:02:30 +0000 (09:02 +0000)
commit4f672a34edfd8440a896d26c28b08ab1d52e5238
tree48ff4cf8be805310a0b33956a8610e09458a0086
parent5779fb61b0d3739aacf74fedbbf1269046291ec1
AMDGPU/SI: Assembler: Unify parsing/printing of operands.

Summary:
The goal is for each operand type to have its own parse function and
at the same time share common code for tracking state as different
instruction types share operand types (e.g. glc/glc_flat, etc).

Introduce parseAMDGPUOperand which can parse any optional operand.
DPP and Clamp/OMod have custom handling for now. Sam also suggested
to have class hierarchy for operand types instead of table. This
can be done in separate change.

Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps,
parseMubufOptionalOps, parseDPPOptionalOps.
Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class.
Rename AsmMatcher/InstPrinter methods accordingly.
Print immediate type when printing parsed immediate operand.
Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3).
Update tests.

Reviewers: tstellarAMD, SamWot, artem.tamazov

Subscribers: qcolombet, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19584

llvm-svn: 268015
35 files changed:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
llvm/test/CodeGen/AMDGPU/ctpop.ll
llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
llvm/test/CodeGen/AMDGPU/global_atomics.ll
llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
llvm/test/CodeGen/AMDGPU/half.ll
llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
llvm/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
llvm/test/CodeGen/AMDGPU/merge-stores.ll
llvm/test/CodeGen/AMDGPU/mubuf.ll
llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
llvm/test/CodeGen/AMDGPU/v_mac.ll
llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
llvm/test/MC/AMDGPU/ds-err.s
llvm/test/MC/AMDGPU/mubuf.s
llvm/test/MC/AMDGPU/reg-syntax-extra.s
llvm/test/MC/Disassembler/AMDGPU/mubuf_vi.txt