[AArch64][SME] Disable ZA LDR/STR addressing optimisations

[AArch64][SME] Disable ZA LDR/STR addressing optimisations

Since the same encoded offset is used for both the vector
select offset and the address offset we have to spot two
patterns simulatenously in the ldr/str intrinsic inputs, i.e.

vector select = base + off
address = base + (off * VL)

whereas currently we only look for the address pattern. I
don't think this is possible in tablegen, so I suspect we'll
have to do this manually as part of lowering or as a target
DAG combine. For now, I've removed these tablegen patterns
so that we at least do the correct thing even if the code
quality isn't great.

I've also changed some of the ldr/str tests to pass in the
same vector select pattern (base + off) as the address
pattern.

Differential Revision: https://reviews.llvm.org/D147433