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[RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instruct...
authorCraig Topper <craig.topper@sifive.com>
Tue, 6 Jun 2023 20:23:17 +0000 (13:23 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 6 Jun 2023 20:23:17 +0000 (13:23 -0700)
commit4f5f38bdabe55ecc8ba18b0a42207341e0bc5d96
tree0388fe29f9a9d41980aedf780bcf6018f548ca54tree | snapshot
parent5f8f310a1ddff967f61ff7f7e023e6961a7e0dd7commit | diff
[RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instructions.

This avoids checking the size of the sequence repeatedly for each
special case. Especially on RV32 where none of the special cases
apply.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152300
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp diff | blob | history
Domain: System / Toolchain;