i965: Implement textureSize (TXS) on Gen4.
authorKenneth Graunke <kenneth@whitecape.org>
Wed, 17 Aug 2011 17:45:47 +0000 (10:45 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 23 Aug 2011 18:18:26 +0000 (11:18 -0700)
commit4eeb4c150598605d1be3ce6674fa63076a720ae9
treeb587cc40dc70fdcbac02bf2d309bc520f7a19882
parentecf8963754489abfb5097c130a9bcd4cdb76b6bd
i965: Implement textureSize (TXS) on Gen4.

Also, remove the BRW_SAMPLER_MESSAGE_SIMD8_RESINFO #define because
there totally isn't a SIMD8 variant.

Unfortunately, resinfo returns FLOAT32 on Broadwater/Crestline, unlike
G45 which returns a proper UINT32.  This turns out to be simple,
however: when we emit MOVs to select the desired half of the SIMD16
result, we can simply override the register type to be float so it's
converted to an integer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp