drm/i915/skl: Do not disable cdclk PLL if csr firmware is present
authorAnimesh Manna <animesh.manna@intel.com>
Tue, 25 Aug 2015 20:06:08 +0000 (01:36 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 30 Sep 2015 08:14:24 +0000 (10:14 +0200)
commit4e961e426cdeb5c9f27d65fb0afb0010fcecfeae
tree9800eb9d99215b095ea6b8094f4933b3a423d7a9
parentc268444a2cecabc0ab567ca275662d80fa0ac813
drm/i915/skl: Do not disable cdclk PLL if csr firmware is present

While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work properly.

v1: Initial version.

v2: Based on review comment from Daniel added code commnent.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-bt: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c