ath9k: Fix RTC_DERIVED_CLK usage
authorMiaoqing Pan <miaoqing@qca.qualcomm.com>
Thu, 6 Nov 2014 05:22:23 +0000 (10:52 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 11 Nov 2014 21:24:18 +0000 (16:24 -0500)
commit4e6ce4dc7ce71d0886908d55129d5d6482a27ff9
tree6f6dbb1181866103987a897801bb615223900072
parent0cd75b19899fd86b51a6480fb8c00dcd85a54591
ath9k: Fix RTC_DERIVED_CLK usage

Based on the reference clock, which could be 25MHz or 40MHz,
AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
But, when a chip reset is done, processing the initvals
sets the register back to the default value.

Fix this by moving the code in ath9k_hw_init_pll() to
ar9003_hw_override_ini(). Also, do this override for AR9531.

Cc: stable@vger.kernel.org
Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_phy.c
drivers/net/wireless/ath/ath9k/hw.c