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(parent: 9aa01c4) | patch
[mlir][gpu][nvvm] fixed bug with literal for inline asm for mma instruction
authorAart Bik <ajcbik@google.com>
Wed, 15 Mar 2023 04:43:20 +0000 (21:43 -0700)
committerAart Bik <ajcbik@google.com>
Fri, 17 Mar 2023 16:22:15 +0000 (09:22 -0700)
commit4e4af1338da5bdbf10e113c0462d7eb7222b5d97
tree6695fb0bbb3f33f34df1ab79ea2da46db3493657tree | snapshot
parent9aa01c4e8917569a7557fe05b278fc0892c9b56acommit | diff
[mlir][gpu][nvvm] fixed bug with literal for inline asm for mma instruction

The 'mma.sp.sync.aligned' family of instructions expects
the sparsity selector as a direct literal (0x0 or 0x1).
The current MLIR inline asm passed this as a value in
register, which broke the downstream assemblers

This is a small step towards supporting 2:4 sparsity on
NVidia GPUs in the sparse compiler of MLIR.

Reviewed By: ThomasRaoux, guraypp

Differential Revision: https://reviews.llvm.org/D146110
mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp diff | blob | history
mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir diff | blob | history
Domain: System / Toolchain;