perf_event: aml pmu interrupt issue fixup

perf_event: aml pmu interrupt issue fixup

PD#167574: perf_event: aml pmu interrupt issue fixup

amlogic arm pmu have a issue that all core's interrupts routes to
one gic SPI interrupt,
when some core raise a pmu interrupt(arm pmu counter overflow),
the global gic SPI interrupt will raise(default on cpu0),
and we can obtain core info which caused interrupt from
sys_cpu_status0 reg.

In global pmu interrupt handler we distinguish interrupts from other cpu,
then send a AML ipi interrupt and wait that cpu complete pmu interrupt.

Change-Id: I28ada689e5b94671c8cfb6189e46134c3c6804cd
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>