aarch64: Relax aarch64_<sur>q<r>shr<u>n2_n<mode> RTL pattern

aarch64: Relax aarch64_<sur>q<r>shr<u>n2_n<mode> RTL pattern

Implement saturating right-shift and narrow high Neon intrinsic RTL
patterns using a vec_concat of a register_operand and a VQSHRN_N
unspec - instead of just a VQSHRN_N unspec. This more relaxed pattern
allows for more aggressive combinations and ultimately better code
generation.

gcc/ChangeLog:

2021-03-04  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n2_n<mode>):
	Implement as an expand emitting a big/little endian
	instruction pattern.
	(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Define.
	(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Define.