RISC-V: Implement instruction patterns for ZBS extension.

RISC-V: Implement instruction patterns for ZBS extension.

2021-10-25  Jim Wilson  <jimw@sifive.com>
	    Kito Cheng  <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/bitmanip.md (shiftm1): New.
	(*bset<mode>): Ditto.
	(*bset<mode>_mask): Ditto.
	(*bset<mode>_1): Ditto.
	(*bset<mode>_1_mask): Ditto.
	(*bseti<mode>): Ditto.
	(*bclr<mode>): Ditto.
	(*bclri<mode>): Ditto.
	(*binv<mode>): Ditto.
	(*binvi<mode>): Ditto.
	(*bext<mode>): Ditto.
	(*bexti): Ditto.
	* config/riscv/predicates.md (splittable_const_int_operand):
	Handle bseti.
	(single_bit_mask_operand): New.
	(not_single_bit_mask_operand): Ditto.
	(const31_operand): Ditto.
	(const63_operand): Ditto.
	* config/riscv/riscv.c (riscv_build_integer_1): Handle bseti.
	(riscv_output_move): Ditto.
	(riscv_print_operand): Handle new operand type: T and S.
	* config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): New.

2021-10-25  Jia-Wei Chen  <jiawei@iscas.ac.cn>
	    Shi-Hua Liao  <shihua@iscas.ac.cn>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zba-slliuw.c: Apply zbs to this testcase.
	* gcc.target/riscv/zbs-bclr.c: New.
	* gcc.target/riscv/zbs-bext.c: Ditto.
	* gcc.target/riscv/zbs-binv.c: Ditto.
	* gcc.target/riscv/zbs-bset.c: Ditto.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>
Co-authored-by: Shi-Hua Liao <shihua@iscas.ac.cn>