MIPS: ath79: rework IP2/IP3 interrupt handling
authorGabor Juhos <juhosg@openwrt.org>
Wed, 14 Mar 2012 09:45:24 +0000 (10:45 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 15 May 2012 15:49:08 +0000 (17:49 +0200)
commit4dbcbdf8135def8f704b130305721bdd42a8078b
treef6b8dec7781a7ece62f55af354ba6f5e49d37fdb
parent5b5b544ed32a1b6ad4d7706fcee530eb67670e71
MIPS: ath79: rework IP2/IP3 interrupt handling

The current implementation assumes that flushing the
DDR writeback buffer is required for IP2/IP3 interrupts,
however this is not true for all SoCs.

Use SoC specific IP2/IP3 handlers instead of flushing
the buffers in the dispatcher code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/ath79/irq.c