opcodes: blackfin: fix decoding of dsp mult insns
authorMike Frysinger <vapier@gentoo.org>
Sun, 13 Feb 2011 18:54:49 +0000 (18:54 +0000)
committerMike Frysinger <vapier@gentoo.org>
Sun, 13 Feb 2011 18:54:49 +0000 (18:54 +0000)
commit4db663940931db273ab59affa3d2af4cfe1e29e7
tree94981e624e82a953aee0da9e1a9d62cd442527aa
parent36f446111a0aba2bbd622ea73a2b5a9a363e5f5c
opcodes: blackfin: fix decoding of dsp mult insns

When assigning to a register half, the mac0 part of the mult insn
was not decoding properly.  It would always show a full dreg instead
of the dreg low half.

Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/testsuite/ChangeLog
gas/testsuite/gas/bfin/arithmetic.d
gas/testsuite/gas/bfin/parallel.d
gas/testsuite/gas/bfin/parallel3.d
gas/testsuite/gas/bfin/vector.d
gas/testsuite/gas/bfin/vector2.d
opcodes/ChangeLog
opcodes/bfin-dis.c