drm/i915: Split color mgmt based on single vs. double buffered registers
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 5 Feb 2019 16:08:40 +0000 (18:08 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 7 Feb 2019 19:45:44 +0000 (21:45 +0200)
commit4d8ed54c044703f96b1df9ef7ac689b18899a470
tree077f1821ef67e824fb616bce4509a2c4e077893f
parent87cefd57c88aecc877b35c89375fe688a8eb0868
drm/i915: Split color mgmt based on single vs. double buffered registers

Split the color management hooks along the single vs. double
buffered registers line. Of the currently programmed registers
GAMMA_MODE and the ilk+ pipe CSC are double buffered, the
LUTS and CHV CGM block are single buffered.

The double buffered register will be programmed during the
normal pipe update with evasion, and also during pipe enable
so that the settings will already be correct when the pipe
starts up before the planes are enabled.

The single buffered registers are currently programmed before
the vblank evade. Which is totally wrong, but we'll correct
that later.

v2: Add some docs to explain the two vfuncs (Matt,Uma)
    Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-6-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_color.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h