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[RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)
authorLiqin Weng <Liqin.Weng@streamcomputing.com>
Wed, 30 Mar 2022 07:57:46 +0000 (15:57 +0800)
committerBen Shi <ben.shi@streamcomputing.com>
Wed, 30 Mar 2022 08:51:09 +0000 (16:51 +0800)
commit4cb85da811243d0a32a909c9e06f18fadd7b76fe
treefc781390e8953dcc3cf29abc329d9582a9c45351tree | snapshot
parent4fec44b0e63d0dcde0897cf55670ccc1748c8654commit | diff
[RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D122702
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td diff | blob | history
llvm/test/CodeGen/RISCV/rv32zbt.ll diff | blob | history
llvm/test/CodeGen/RISCV/rv64zbt.ll diff | blob | history
Domain: System / Toolchain;