[X86][Costmodel] Load/store i32/f32 Stride=3 VF=16 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 11:23:13 +0000 (14:23 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 11:34:19 +0000 (14:34 +0300)
commit4ca5bc07af0685fbbe04e8731b4ab37354368c84
tree1f7aea6c6e9b848420d3c81a33eb43795aa6820b
parent198aa84973e6d5f9cdc7b241c4dc9880d63a5b5c
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=16 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/5fqrh4qqo - for intels `Block RThroughput: =14.0`; for ryzens, `Block RThroughput: <=12.0`
So pick cost of `14`.

For store we have:
https://godbolt.org/z/5fqrh4qqo - for intels `Block RThroughput: =22.0`; for ryzens, `Block RThroughput: <=16.0`
So pick cost of `22`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111022
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll