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[PowerPC] Reduce symmetrical swaps for lane-insensitive vector ops
authorQiu Chaofan <qiucofan@cn.ibm.com>
Wed, 10 Mar 2021 07:21:32 +0000 (15:21 +0800)
committerQiu Chaofan <qiucofan@cn.ibm.com>
Wed, 10 Mar 2021 07:21:32 +0000 (15:21 +0800)
commit4c973ae51b859dca9792e1ad87a6673c49815a8d
tree194c140d98b8a02058eaee7e08a8de42686b94f2tree | snapshot
parentcd6d1799adfc589626917bce968f33cca821a129commit | diff
[PowerPC] Reduce symmetrical swaps for lane-insensitive vector ops

This patch simplifies pattern (xxswap (vec-op (xxswap a) (xxswap b)))
into (vec-op a b) if vec-op is lane-insensitive. The motivating case
is ScalarToVector-VecOp-ExtractElement sequence on LE, but the
peephole itself is not related to endianness, so BE may also benefit
from this.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D97658
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/PowerPC/swap-reduction.ll [new file with mode: 0644] blob
Domain: System / Toolchain;