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[llvm][SVE] Remove redundant and when comparing against extending load
authorDavid Truby <david.truby@arm.com>
Tue, 19 Jul 2022 13:13:10 +0000 (14:13 +0100)
committerDavid Truby <david.truby@arm.com>
Tue, 19 Jul 2022 16:08:32 +0000 (17:08 +0100)
commit4c82f56d8fb9266f46d11c293aa10f53153ecf69
tree06f1e95d985269e10e809f3734a17f1461ddef00tree | snapshot
parent8c6305b8b485c26d52409790ffdabe0898af81a1commit | diff
[llvm][SVE] Remove redundant and when comparing against extending load

When determining if an `and` should be merged into an extending load
the constant argument to the `and` is currently not checked if the
argument requires truncation. This prevents the combine happening when
the vector width is half the normal available vector width for SVE VLA
vectors.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D129281
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/AArch64/sve-extload-icmp.ll [new file with mode: 0644] blob
Domain: System / Toolchain;