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[ARM][LowOverheadLoops] Ensure memory predication
authorSam Parker <sam.parker@arm.com>
Wed, 5 Feb 2020 12:47:03 +0000 (12:47 +0000)
committerSam Parker <sam.parker@arm.com>
Wed, 5 Feb 2020 13:19:08 +0000 (13:19 +0000)
commit4c7f819204d8c52a25cc98a083791ad9db7d1ad9
tree19a4b983c90b17fdc8af2082308b7456b5d1ba99tree | snapshot
parent706256b6d3972dcfa2d3e888d0640e1689c4be95commit | diff
[ARM][LowOverheadLoops] Ensure memory predication

While validating each MVE instruction, check that all instructions
that touch memory are somehow predicated upon the VCTP.

Differential Revision: https://reviews.llvm.org/D73616
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir [new file with mode: 0644] blob
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir [new file with mode: 0644] blob
Domain: System / Toolchain;