GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM
authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Wed, 10 Mar 2021 12:33:10 +0000 (18:03 +0530)
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Wed, 10 Mar 2021 13:16:07 +0000 (18:46 +0530)
commit4c6ab48fb1149c4f1f1d2953f5d232211b3a6bce
treea6c2190305e8bdbef4d6e36d7ee3b34de4c125bb
parent99b01cf28db9db1a3ec0e25367bd325b7aca6d43
GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM

It is good to have a combined `divrem` instruction when the
`div` and `rem` are computed from identical input operands.
Some targets can lower them through a single expansion that
computes both division and remainder. It effectively reduces
the number of instructions than individually expanding them.

Reviewed By: arsenm, paquette

Differential Revision: https://reviews.llvm.org/D96013
12 files changed:
llvm/docs/GlobalISel/GenericOpcode.rst
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/GenericOpcodes.td
llvm/include/llvm/Target/GlobalISel/Combine.td
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir [new file with mode: 0644]
llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp