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(parent: 4a32581) | patch
[RISCV] Add support for custom instructions for Sifive S76.
authorGarvit Gupta <quic_garvgupt@quicinc.com>
Mon, 26 Jun 2023 18:36:00 +0000 (11:36 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 26 Jun 2023 18:36:00 +0000 (11:36 -0700)
commit4c37d30e22ae655394c8b3a7e292c06d393b9b44
tree386e546dd9e5de66d64262966322eb2a1af84a18tree | snapshot
parent4a32581f3dc74a01c3981b51c7dcf66fd7305c00commit | diff
[RISCV] Add support for custom instructions for Sifive S76.

Support for below instruction is added
1. CFLUSH.D.L1
2. CDISCARD.D.L1
3. CEASE

Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.

Spec - https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153370
clang/test/Driver/riscv-cpus.c diff | blob | history
llvm/docs/RISCVUsage.rst diff | blob | history
llvm/docs/ReleaseNotes.rst diff | blob | history
llvm/lib/Support/RISCVISAInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVFeatures.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td diff | blob | history
llvm/lib/Target/RISCV/RISCVProcessors.td diff | blob | history
llvm/test/MC/RISCV/attribute-arch.s diff | blob | history
llvm/test/MC/RISCV/xsfcie-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/xsfcie-valid.s [new file with mode: 0644] blob
Domain: System / Toolchain;