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RISC-V: add consecutive_bits_operand predicate
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 24 May 2022 13:03:47 +0000 (15:03 +0200)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 14 Jun 2022 11:35:49 +0000 (13:35 +0200)
commit4bf0dcb0492c40be7e0603b13a8b5949609388dd
tree91e6e0202c1f56ae5cc23a79882b3878b00b89aftree | snapshot
parente07a876c07601e1f3a27420f7d055d20193c362ccommit | diff
RISC-V: add consecutive_bits_operand predicate

Provide an easy way to constrain for constants that are a a single,
consecutive run of ones.

gcc/ChangeLog:

* config/riscv/predicates.md (consecutive_bits_operand):
Implement new predicate.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gcc/config/riscv/predicates.md diff | blob | history
Domain: System / Toolchain;